We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
Adnan Aziz, Felice Balarin, Robert K. Brayton, Alb...
Abstract. While effective methods for bit-level verification of low-level properties exist, system-level properties that entail reasoning about a significant part of the design p...
Panagiotis Manolios, Sudarshan K. Srinivasan, Daro...
We present a constructive authorization logic where the meanings of connectives are defined by their associated inference rules. This ensures that the logical reading of access c...
We present a system (ASP − PROLOG) which provides a tight and well-defined integration of Prolog and Answer Set Programming (ASP). The combined system enhances the expressive po...