82 search results - page 4 / 17 » Design of Asynchronous Controllers with Delay Insensitive In... |
MEMOCODE
2007
IEEE
14 years 1 months ago
2007
IEEE
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
CDES
2009
13 years 8 months ago
2009
This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This ne...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
DATE
2010
IEEE
14 years 17 days ago
2010
IEEE
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...