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ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Design and design automation of rectification logic for engineering change
In a later stage of a VLSI design, it is quite often to modify a design implementation to accommodate the new specification, design errors, or to meet design constraints. In addit...
Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang...
TPDS
2010
260views more  TPDS 2010»
13 years 6 months ago
Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
Yongji Zhou, T. X. Mei, Steven Freear
OSN
2011
12 years 10 months ago
A parallel iterative scheduler for asynchronous Optical Packet Switching networks
—This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. O...
Pablo Pavón-Mariño, M. Victoria Buen...
CSREAESA
2006
13 years 9 months ago
Design and Implementation of SoPC with Multi-Bus on a Chip
SoPC (System on a Programmable Chip) is one important kind of SoC solution based on PLD (Programmable Logic Device). At the same time, PBD (Platform-based Design) has become popul...
Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang,...
FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
13 years 11 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith