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EUC
2006
Springer
14 years 9 days ago
Co-optimization of Performance and Power in a Superscalar Processor Design
Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. Th...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 10 months ago
An integrated performance and power model for superscalar processor designs
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
EHCI
2001
13 years 10 months ago
Modelling and Using Sensed Context Information in the Design of Interactive Applications
We present a way of analyzing sensed context information formulated to help in the generation, documentation and assessment of the designs of context-aware applications. Starting w...
Philip D. Gray, Daniel Salber
IJNSEC
2008
106views more  IJNSEC 2008»
13 years 8 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
ICASSP
2008
IEEE
14 years 3 months ago
Automatic synthesis of VLSI architectures for arbitrary lifting-based filter banks and transforms
Recently, the conventional lifting scheme that is widely used for the construction of Wavelets and 2-channel filter banks has been extended to M-channel filter banks (M > 2)....
Ruben Bartholomä, Thomas Greiner, Frank Kesel...