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» Design space exploration for 3D architectures
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ASPDAC
2006
ACM
124views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Functional modeling techniques for efficient SW code generation of video codec applications
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya
CCR
2008
88views more  CCR 2008»
13 years 8 months ago
Rethinking virtual network embedding: substrate support for path splitting and migration
Network virtualization is a powerful way to run multiple architectures or experiments simultaneously on a shared infrastructure. However, making efficient use of the underlying re...
Minlan Yu, Yung Yi, Jennifer Rexford, Mung Chiang
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 2 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
CEE
2007
110views more  CEE 2007»
13 years 8 months ago
HW/SW co-design for public-key cryptosystems on the 8051 micro-controller
It is a challenge to implement large word length public-key algorithms on embedded systems. Examples are smartcards, RF-ID tags and mobile terminals. This paper presents a HW/SW c...
Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid...
ISPASS
2007
IEEE
14 years 2 months ago
Cross Binary Simulation Points
Architectures are usually compared by running the same workload on each architecture and comparing performance. When a single compiled binary of a program is executed on many diff...
Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jal...