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» Design space exploration revisited
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ASAP
2007
IEEE
175views Hardware» more  ASAP 2007»
15 years 7 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S...
154
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COORDINATION
2008
Springer
15 years 7 months ago
Actors with Multi-headed Message Receive Patterns
Abstract. The actor model provides high-level concurrency abstractions to coordinate simultaneous computations by message passing. Languages implementing the actor model such as Er...
Martin Sulzmann, Edmund S. L. Lam, Peter Van Weert
AAAI
2004
15 years 7 months ago
Methods for Boosting Revenue in Combinatorial Auctions
We study the recognized open problem of designing revenuemaximizing combinatorial auctions. It is unsolved even for two bidders and two items for sale. Rather than pursuing the pu...
Anton Likhodedov, Tuomas Sandholm
JRTIP
2008
249views more  JRTIP 2008»
15 years 6 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...
SIGMETRICS
2008
ACM
15 years 5 months ago
An SLA perspective on the router buffer sizing problem
In this paper, we discuss recent work on buffer sizing in the context of an ISP's need to offer and guarantee competitive Service Level Agreements (SLAs) to its customers. Si...
Joel Sommers, Paul Barford, Albert G. Greenberg, W...