Sciweavers

2945 search results - page 106 / 589
» Designing and Implementing Malicious Hardware
Sort
View
141
Voted
VLSISP
2008
123views more  VLSISP 2008»
15 years 4 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
139
Voted
ICPP
2009
IEEE
15 years 11 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
FPL
2005
Springer
79views Hardware» more  FPL 2005»
15 years 10 months ago
FPGA-based implementation and comparison of recursive and iterative algorithms
The paper analyses and compares alternative iterative and recursive implementations of FPGA circuits for various problems. Two types of recursive calls have been examined, namely ...
Valery Sklyarov, Iouliia Skliarova, Bruno Figueire...
VEE
2006
ACM
142views Virtualization» more  VEE 2006»
15 years 10 months ago
Secure and practical defense against code-injection attacks using software dynamic translation
One of the most common forms of security attacks involves exploiting a vulnerability to inject malicious code into an executing application and then cause the injected code to be ...
Wei Hu, Jason Hiser, Daniel Williams, Adrian Filip...
MSS
2000
IEEE
79views Hardware» more  MSS 2000»
15 years 9 months ago
A Scalable Architecture for Maximizing Concurrency
This paper describes a design that addresses limitations inherent in the initial implementation of the Archive for the Earth Observing Systems (EOS). The design consists of two el...
Jonathan Crawford