2945 search results - page 500 / 589 » Designing and Implementing Malicious Hardware |
150
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SIGCOMM
2009
ACM
16 years 15 days ago
2009
ACM
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
157
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ISCA
2007
IEEE
16 years 9 days ago
2007
IEEE
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
167
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MICRO
2005
IEEE
15 years 11 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
206
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SBACPAD
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper discusses the implementation of a numerical algorithm for simulating incompressible fluid flows based on the finite difference method and designed for parallel compu...
167
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MICRO
2002
IEEE
15 years 11 months ago
2002
IEEE
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...