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CAV
1998
Springer
175views Hardware» more  CAV 1998»
13 years 11 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
ECBS
1996
IEEE
127views Hardware» more  ECBS 1996»
13 years 11 months ago
Domain Engineering: The Challenge, Status, and Trends
Naval Surface Warfare Center Dahlgren Division; under joint sponsorship of the Office of Naval Research; the Naval Command, Control, and Ocean Surveillance Center; and the Naval S...
Stephanie White, Michael Edwards
ANCS
2007
ACM
13 years 10 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
IPSN
2010
Springer
13 years 10 months ago
Practical modeling and prediction of radio coverage of indoor sensor networks
The robust operation of many sensor network applications depends on deploying relays to ensure wireless coverage. Radio mapping aims to predict network coverage based on a small n...
Octav Chipara, Gregory Hackmann, Chenyang Lu, Will...
CIKM
2006
Springer
13 years 10 months ago
Structure-based querying of proteins using wavelets
The ability to retrieve molecules based on structural similarity has use in many applications, from disease diagnosis and treatment to drug discovery and design. In this paper, we...
Keith Marsolo, Srinivasan Parthasarathy, Kotagiri ...