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DFT
2005
IEEE
110views VLSI» more  DFT 2005»
15 years 9 months ago
A design flow for protecting FPGA-based systems against single event upsets
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
Luca Sterpone, Massimo Violante
IEAAIE
2004
Springer
15 years 9 months ago
Knowledge Representation on Design of Storm Drainage System
During the design of storm drainage system, many decisions are involved on the basis of rules of thumb, heuristics, judgment, code of practice and previous experience of the design...
Kwok-wing Chau, C. S. Cheung
GLVLSI
2003
IEEE
229views VLSI» more  GLVLSI 2003»
15 years 9 months ago
Design issues in low-voltage high-speed current-mode logic buffers
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain ...
Payam Heydari
DAGM
2008
Springer
15 years 5 months ago
Novel VQ Designs for Discrete HMM On-Line Handwritten Whiteboard Note Recognition
In this work we propose two novel vector quantization (VQ) designs for discrete HMM-based on-line handwriting recognition of whiteboard notes. Both VQ designs represent the binary ...
Joachim Schenk, Stefan Schwärzler, Günth...
WCE
2007
15 years 5 months ago
Stochastic Urban Rapid Transit Network Design
— The rapid transit network design problem considers at upper level the list of potential transit corridors and stations to design the network as a discrete space of alternatives...
Carlos Bouza, Gemayzel Bouza, Ángel Mar&iac...