27 search results - page 2 / 6 » Designing real-time H.264 decoders with dataflow architectur... |
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The ha...
TVLSI
2008
13 years 6 months ago
2008
In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result s...
APCCAS
2006
IEEE
14 years 29 days ago
2006
IEEE
We described an H.264 decoder implemented with our design methodology, in which a system function model of transaction level is first captured in SystemC and refined into RTL with ...
ICMCS
2005
IEEE
14 years 15 days ago
2005
IEEE
This paper studied an H.264 HDTV decoder on two multiprocessor system-on-chip architectures. Two types of networks-on-chip, the RAW network and the applicationspecific networks-on...
ASPDAC
2006
ACM
14 years 26 days ago
2006
ACM
- We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant...