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» Designing secure systems on reconfigurable hardware
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ERSA
2010
153views Hardware» more  ERSA 2010»
13 years 5 months ago
VAPRES: A Customizable and Flexible Base Architecture for Partially Reconfigurable Systems
- Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requiremen...
Ann Gordon-Ross, Abelardo Jara-Berrocal
FPL
2003
Springer
89views Hardware» more  FPL 2003»
14 years 24 days ago
Reconfigurable Systems in Education
This paper describes methods and tools that have been used for teaching disciplines dedicated to the design of reconfigurable digital systems. It demonstrates students' projec...
Valery Sklyarov, Iouliia Skliarova
COMPSAC
2004
IEEE
13 years 11 months ago
Services-Oriented Dynamic Reconfiguration Framework for Dependable Distributed Computing
Web services (WS) received significant attention recently because services can be searched, bound, and executed at runtime over the Internet. This paper proposes a dynamic reconfi...
Wei-Tek Tsai, Weiwei Song, Raymond A. Paul, Zhibin...
FPL
2007
Springer
80views Hardware» more  FPL 2007»
14 years 1 months ago
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi,...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan