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» Designing secure systems on reconfigurable hardware
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ASAP
2009
IEEE
98views Hardware» more  ASAP 2009»
13 years 5 months ago
A Power-Scalable Switch-Based Multi-processor FFT
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M pr...
Bassam Jamil Mohd, Earl E. Swartzlander Jr.
FPL
2008
Springer
112views Hardware» more  FPL 2008»
13 years 9 months ago
Secure FPGA configuration architecture preventing system downgrade
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a syst...
Benoît Badrignans, Reouven Elbaz, Lionel Tor...
DAC
2004
ACM
13 years 11 months ago
An SoC design methodology using FPGAs and embedded microprocessors
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
Nobuyuki Ohba, Kohji Takano
PROCEDIA
2010
138views more  PROCEDIA 2010»
13 years 2 months ago
Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics
Currently several computational problems require high processing power to handle huge amounts of data, although underlying core algorithms appear to be rather simple. Especially i...
Lars Wienbrandt, Stefan Baumgart, Jost Bissel, Car...
TEI
2009
ACM
117views Hardware» more  TEI 2009»
14 years 2 months ago
Easigami: a reconfigurable folded-sheet TUI
Easigami is a novel tangible user interface (TUI) and interactive system intended to help children to learn to fold 3D geometric forms and to explore 2D-3D transformations. We pre...
Yingdan Huang, Mark D. Gross, Ellen Yi-Luen Do, Mi...