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ICS
2003
Tsinghua U.
14 years 22 days ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
OOPSLA
2010
Springer
13 years 5 months ago
Composable specifications for structured shared-memory communication
In this paper we propose a communication-centric approach to specifying and checking how multithreaded programs use shared memory to perform inter-thread communication. Our approa...
Benjamin P. Wood, Adrian Sampson, Luis Ceze, Dan G...
IPPS
2008
IEEE
14 years 1 months ago
Scaling alltoall collective on multi-core systems
MPI Alltoall is one of the most communication intense collective operation used in many parallel applications. Recently, the supercomputing arena has witnessed phenomenal growth o...
Rahul Kumar, Amith R. Mamidala, Dhabaleswar K. Pan...
ASPLOS
2008
ACM
13 years 9 months ago
Concurrency control with data coloring
Concurrency control is one of the main sources of error and complexity in shared memory parallel programming. While there are several techniques to handle concurrency control such...
Luis Ceze, Christoph von Praun, Calin Cascaval, Pa...
TC
2010
13 years 5 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...