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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
14 years 1 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
IPPS
2006
IEEE
14 years 2 months ago
Exploiting programmable network interfaces for parallel query execution in workstation clusters
Workstation clusters equipped with high performance interconnect having programmable network processors facilitate interesting opportunities to enhance the performance of parallel...
V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. ...
HPCC
2009
Springer
14 years 25 days ago
Load Scheduling Strategies for Parallel DNA Sequencing Applications
This paper studies a load scheduling strategy with nearoptimal processing time leveraging the computational characteristics of parallel DNA sequence alignment algorithms, specific...
Sudha Gunturu, Xiaolin Li, Laurence Tianruo Yang
ISCAS
2011
IEEE
342views Hardware» more  ISCAS 2011»
12 years 11 months ago
Parallel Dynamic Voltage and Frequency Scaling for stream decoding using a multicore embedded system
—Parallel structures may be used to increase a system processing speed in case of large amount of data or highly complex calculations. Dynamic Voltage and Frequency Scaling (DVFS...
Ying-Xun Lai, Yueh-Min Huang, Chin-Feng Lai, Ljilj...
ICMCS
2006
IEEE
108views Multimedia» more  ICMCS 2006»
14 years 2 months ago
Image Segmentation using Parallel Self Organizing Tree Map
At present, the researchers are making great effort to search for a general purpose resolution for image segmentation. Most of the approaches we are using now are somewhat ineffic...
Xiaoming Fan, Jonathan Randall, Ivan Lee