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» Diagonal routing in high performance microprocessor design
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AINA
2007
IEEE
14 years 2 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
TCAD
2008
119views more  TCAD 2008»
13 years 8 months ago
Full-Chip Routing Considering Double-Via Insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
14 years 1 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
14 years 5 months ago
FastRoute: a step to integrate global routing into placement
Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect inf...
Min Pan, Chris C. N. Chu
MSWIM
2005
ACM
14 years 2 months ago
Randomized energy aware routing algorithms in mobile ad hoc networks
We consider the problem of energy aware localized routing in ad hoc networks. In localized routing algorithms, each node forwards a message based on the position information about...
Israat Tanzeena Haque, Chadi Assi, J. William Atwo...