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» Diagonal routing in high performance microprocessor design
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MOBICOM
2005
ACM
14 years 29 days ago
Architecture and evaluation of an unplanned 802.11b mesh network
This paper evaluates the ability of a wireless mesh architecture to provide high performance Internet access while demanding little deployment planning or operational management. ...
John C. Bicket, Daniel Aguayo, Sanjit Biswas, Robe...
DAC
2005
ACM
13 years 9 months ago
How accurately can we model timing in a placement engine?
This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate ...
Amit Chowdhary, Karthik Rajagopal, Satish Venkates...
TPDS
2002
105views more  TPDS 2002»
13 years 7 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
HIPC
2007
Springer
14 years 1 months ago
FFTC: Fastest Fourier Transform for the IBM Cell Broadband Engine
The Fast Fourier Transform (FFT) is of primary importance and a fundamental kernel in many computationally intensive scientific applications. In this paper we investigate its perf...
David A. Bader, Virat Agarwal
SIGMETRICS
2000
ACM
217views Hardware» more  SIGMETRICS 2000»
13 years 7 months ago
Experimenting with an Ad Hoc wireless network on campus: insights and experiences
Ad hoc wireless networks are new communication networks that can be dynamically formed and deformed onthe- y, anytime and anywhere. User data is routed with the help of an ad hoc ...
Chai-Keong Toh, Richard Chen, Minar Delwar, Donald...