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ICS
2009
Tsinghua U.
14 years 1 days ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
SIAMCOMP
2000
118views more  SIAMCOMP 2000»
13 years 7 months ago
Constructive, Deterministic Implementation of Shared Memory on Meshes
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with m polynomial in n, where each mesh node hosts a processor and a memory module. A...
Andrea Pietracaprina, Geppino Pucci, Jop F. Sibeyn
ICS
2003
Tsinghua U.
14 years 20 days ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
GECCO
2005
Springer
161views Optimization» more  GECCO 2005»
14 years 1 months ago
Autonomous navigation system applied to collective robotics with ant-inspired communication
Research in collective robotics is motivated mainly by the possibility of achieving an efficient solution to multi-objective navigation tasks when multiple robots are employed, in...
Renato Reder Cazangi, Fernando J. Von Zuben, Maur&...
ICDE
2007
IEEE
182views Database» more  ICDE 2007»
14 years 8 months ago
DIKNN: An Itinerary-based KNN Query Processing Algorithm for Mobile Sensor Networks
Current approaches to K Nearest Neighbor (KNN) search in mobile sensor networks require certain kind of indexing support. This index could be either a centralized spatial index or...
Shan-Hung Wu, Kun-Ta Chuang, Chung-Min Chen, Ming-...