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HPCA
1997
IEEE
14 years 16 days ago
Design Issues and Tradeoffs for Write Buffers
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
Kevin Skadron, Douglas W. Clark
ICDCS
1997
IEEE
14 years 16 days ago
Multi-threading and Remote Latency in Software DSMs
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
Kritchalach Thitikamol, Peter J. Keleher
ICDCS
1994
IEEE
14 years 13 days ago
Management of Updates in the Enhanced Client-Server DBMS
The Client Server DBMS model has emerged as the main paradigm in database computing. The Enhanced Client Server architecture takes advantage of all the available client resources ...
Alex Delis, Nick Roussopoulos
PSC
1992
14 years 11 days ago
A Message Passing Implementation of Lazy Task Creation
Abstract. This paper describes an implementation technique for Multilisp's future construct aimed at large shared-memory multiprocessors. The technique is a variant of lazy ta...
Marc Feeley
EUROPAR
2008
Springer
13 years 10 months ago
Exploration of the Influence of Program Inputs on CMP Co-scheduling
Recent studies have showed the effectiveness of job co-scheduling in alleviating shared-cache contention on Chip Multiprocessors. Although program inputs affect cache usage and thu...
Yunlian Jiang, Xipeng Shen