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IPPS
2006
IEEE
15 years 8 months ago
Helper thread prefetching for loosely-coupled multiprocessor systems
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an in...
Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihi...
MSS
2005
IEEE
106views Hardware» more  MSS 2005»
15 years 8 months ago
An Architecture for Lifecycle Management in Very Large File Systems
We present a policy-based architecture STEPS for lifecycle management (LCM) in a mass scale distributed file system. The STEPS architecture is designed in the context of IBM’s ...
Akshat Verma, David Pease, Upendra Sharma, Marc Ka...
IEEEPACT
2002
IEEE
15 years 7 months ago
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, ...
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasu...
PDP
2010
IEEE
15 years 6 months ago
hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
François Broquedis, Jérôme Cle...
HPCA
1999
IEEE
15 years 6 months ago
Improving CC-NUMA Performance Using Instruction-Based Prediction
We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior o...
Stefanos Kaxiras, James R. Goodman