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ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
ICS
2009
Tsinghua U.
14 years 2 months ago
Access map pattern matching for data cache prefetch
Yasuo Ishii, Mary Inaba, Kei Hiraki
EUROPAR
2004
Springer
14 years 1 months ago
Contents Management in First-Level Multibanked Data Caches
Enrique F. Torres, Pablo Ibáñez, V&i...
ICS
2004
Tsinghua U.
14 years 1 months ago
Detailed cache coherence characterization for OpenMP benchmarks
Jaydeep Marathe, Anita Nagarajan, Frank Mueller
EUROPAR
2003
Springer
14 years 1 months ago
Counteracting Bank Misprediction in Sliced First-Level Caches
Enrique F. Torres, Pablo Ibáñez, V&i...