Sciweavers

22 search results - page 3 / 5
» Dominance Testing via Model Checking
Sort
View
ICSE
2001
IEEE-ACM
14 years 2 days ago
Fast Formal Analysis of Requirements via "Topoi Diagrams"
Early testing of requirements can decrease the cost of removing errors in software projects. However, unless done carefully, that testing process can significantly add to the cos...
Tim Menzies, John D. Powell, Michael E. Houle
IFIP
2001
Springer
14 years 2 days ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
FAC
2008
114views more  FAC 2008»
13 years 7 months ago
Specification of communicating processes: temporal logic versus refusals-based refinement
Abstract. In this paper we consider the relationship between refinement-oriented specification and specifications using a temporal logic. We investigate the extent to which one can...
Gavin Lowe
BELL
2000
107views more  BELL 2000»
13 years 7 months ago
Automating software feature verification
A significant part of the call processing software for Lucent's new PathStar access server [FSW98] was checked with automated formal verification techniques. The verification...
Gerard J. Holzmann, Margaret H. Smith
ICDCS
2010
IEEE
13 years 11 months ago
Sentomist: Unveiling Transient Sensor Network Bugs via Symptom Mining
—Wireless Sensor Network (WSN) applications are typically event-driven. While the source codes of these applications may look simple, they are executed with a complicated concurr...
Yangfan Zhou, Xinyu Chen, Michael R. Lyu, Jiangchu...