Sciweavers

212 search results - page 41 / 43
» Dynamic Logic with Non-rigid Functions
Sort
View
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 3 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
EMSOFT
2007
Springer
14 years 1 months ago
Proving the absence of run-time errors in safety-critical avionics code
We explain the design of the interpretation-based static analyzer Astr´ee and its use to prove the absence of run-time errors in safety-critical codes. Categories and Subject Des...
Patrick Cousot
VRCAI
2004
ACM
14 years 11 days ago
Explorative construction of virtual worlds: an interactive kernel approach
Despite steady research advances in many aspects of virtual reality, building and testing virtual worlds remains to be a very difficult process. Most virtual environments are stil...
Jinseok Seo, Gerard Jounghyun Kim
DOLAP
2003
ACM
14 years 6 days ago
Achieving adaptivity for OLAP-XML federations
Motivated by the need for more flexible OLAP systems, this paper presents work on logical integration of external data in OLAP databases, carried out in cooperation between the D...
Dennis Pedersen, Torben Bach Pedersen
INFOCOM
1999
IEEE
13 years 11 months ago
Enhancing Survivability of Mobile Internet Access Using Mobile IP with Location Registers
The Mobile IP (MIP) protocol for IP version 4 provides continuous Internet connectivity to mobile hosts. However, currently it has some drawbacks in the areas of survivability, per...
Ravi Jain, Thomas Raleigh, Danny Yang, Li-Fung Cha...