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» Dynamic Memory Design for Low Data-Retention Power
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ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
14 years 2 months ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
ICMCS
2005
IEEE
158views Multimedia» more  ICMCS 2005»
14 years 2 months ago
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolan...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 1 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
CHI
2000
ACM
14 years 1 months ago
Power browser: efficient Web browsing for PDAs
We have designed and implemented new Web browsing facilities to support effective navigation on Personal Digital Assistants (PDAs) with limited capabilities: low bandwidth, small ...
Orkut Buyukkokten, Hector Garcia-Molina, Andreas P...
DAC
2009
ACM
14 years 9 months ago
Enabling adaptability through elastic clocks
Power and performance benefits of scaling are lost to worst case margins as uncertainty of device characteristics is increasing. Adaptive techniques can dynamically adjust the mar...
Emre Tuncer, Jordi Cortadella, Luciano Lavagno