In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
Mohamed A. Gomaa, Michael D. Powell, T. N. Vijayku...
In object oriented languages, dynamic memory allocation is a fundamental concept. When using such a language in hard real-time systems, it becomes important to bound both the worst...
Wolfgang Puffitsch, Benedikt Huber, Martin Schoebe...
— Sharing of 3G network infrastructure among operators offers an alternative solution to reducing the investment in the coverage phase of WCDMA. For radio access network (RAN) sh...
Salman AlQahtani, Ashraf S. Mahmoud, Asrar U. Shei...