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SAC
2008
ACM
13 years 6 months ago
Exploiting program cyclic behavior to reduce memory latency in embedded processors
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
Ehsan Atoofian, Amirali Baniasadi
CASES
2009
ACM
14 years 1 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
ASPLOS
2004
ACM
14 years 25 days ago
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
Mohamed A. Gomaa, Michael D. Powell, T. N. Vijayku...
ISOLA
2010
Springer
13 years 5 months ago
Worst-Case Analysis of Heap Allocations
In object oriented languages, dynamic memory allocation is a fundamental concept. When using such a language in hard real-time systems, it becomes important to bound both the worst...
Wolfgang Puffitsch, Benedikt Huber, Martin Schoebe...
ICC
2007
IEEE
147views Communications» more  ICC 2007»
14 years 1 months ago
Performance Analysis of Adaptive Rate Scheduling Scheme for 3G WCDMA Wireless Networks with Multi-Operators
— Sharing of 3G network infrastructure among operators offers an alternative solution to reducing the investment in the coverage phase of WCDMA. For radio access network (RAN) sh...
Salman AlQahtani, Ashraf S. Mahmoud, Asrar U. Shei...