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ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
14 years 27 days ago
Power-performance trade-off using pipeline delays
— We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are ...
G. Surendra, Subhasis Banerjee, S. K. Nandy
CONCURRENCY
2010
172views more  CONCURRENCY 2010»
13 years 4 months ago
Modeling of tsunami waves and atmospheric swirling flows with graphics processing unit (GPU) and radial basis functions (RBF)
The faster growth curves in the speed of GPUs relative to CPUs in the past decade and its rapidly gained popularity have spawned a new area of development in computational technol...
Jessica Schmidt, Cécile Piret, Nan Zhang, B...
ISPASS
2005
IEEE
14 years 1 months ago
Partitioning Multi-Threaded Processors with a Large Number of Threads
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
Ali El-Moursy, Rajeev Garg, David H. Albonesi, San...
PDPTA
2000
13 years 8 months ago
The KIT COSMOS Processor: Introducing CONDOR
Abstract In this paper, we propose a microprocessor architecture which eciently utilizes nextgeneration semiconductor technology. While the technology makes it possible to integrat...
Toshinori Sato, Itsujiro Arita
VEE
2012
ACM
187views Virtualization» more  VEE 2012»
12 years 3 months ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...