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126
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EUROPAR
2001
Springer
15 years 6 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
107
Voted
IPPS
2000
IEEE
15 years 6 months ago
A Parallel Co-evolutionary Metaheuristic
In order to show that the parallel co-evolution of di erent heuristic methods may lead to an e cient search strategy, we have hybridized three heuristic agents of complementary beh...
Vincent Bachelet, El-Ghazali Talbi
BIRTHDAY
2000
Springer
15 years 6 months ago
FFF97 - Oberon in the Real World
The Oberon programming language and system, subsequently called the Oberon technology, are well known in the software research community. Few applications, however, exist outside ...
Josef Templ
PDP
2010
IEEE
15 years 6 months ago
hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
François Broquedis, Jérôme Cle...
HCW
1999
IEEE
15 years 6 months ago
Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata
A framework for task assignment in heterogeneous computing systems is presented in this work. The framework is based on a learning automata model. The proposed model can be used f...
Raju D. Venkataramana, N. Ranganathan