1341 search results - page 109 / 269 » Dynamic Testimonial Logic |
SCCC
1998
IEEE
14 years 1 months ago
1998
IEEE
The last few years have seen a renewal of interest in the consideration of dynamic programming in compiler technology. This is due to the compactness of the representations, which...
POPL
2005
ACM
14 years 9 months ago
2005
ACM
We present a new approach to partial-order reduction for model checking software. This approach is based on initially exploring an arbitrary interleaving of the various concurrent...
CIA
2007
Springer
14 years 3 months ago
2007
Springer
Recognizing that trust states are mental states, this paper presents a formal analysis of the dynamics of trust in terms of the functional roles and representation relations for tr...
FPT
2005
IEEE
14 years 2 months ago
2005
IEEE
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...