25 search results - page 5 / 5 » Dynamic hardware plugins in an FPGA with partial run-time re... |
ERSA
2006
13 years 8 months ago
2006
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
JSA
2002
13 years 6 months ago
2002
This paper examines some models of FSMs that can be implemented in dynamically and statically reconfigurable FPGAs. They enable circuits for the FSMs to be constructed in such a wa...
FPL
2008
Springer
13 years 8 months ago
2008
Springer
A high-speed and secure dynamic partial reconfiguration (DPR) system is realized with AES-GCM that guarantees both confidentiality and authenticity of FPGA bitstreams. In DPR syst...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
FPGA
2001
ACM
13 years 11 months ago
2001
ACM
A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extend...