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SDL
2003
147views Hardware» more  SDL 2003»
13 years 9 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
JCC
2007
121views more  JCC 2007»
13 years 7 months ago
Speeding up parallel GROMACS on high-latency networks
: We investigate the parallel scaling of the GROMACS molecular dynamics code on Ethernet Beowulf clusters and what prerequisites are necessary for decent scaling even on such clust...
Carsten Kutzner, David van der Spoel, Martin Fechn...
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
14 years 1 months ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam
ICON
2007
IEEE
14 years 1 months ago
Erlang B as a Performance Model for IP Flows
— Flow-based networking has gained momentum in the research community in recent years. It allows improved performance guarantees and dynamic, load-aware routing. Flowbased networ...
Alexander A. Kist
ICDCS
2011
IEEE
12 years 7 months ago
Delay-Cognizant Reliable Delivery for Publish/Subscribe Overlay Networks
—The number of real-world applications that require QoS guarantees is constantly increasing and they often follow the publish/subscribe (pub/sub) messaging paradigm, which provid...
Shuo Guo, Kyriakos Karenos, Minkyong Kim, Hui Lei,...