130 search results - page 20 / 26 » Dynamically Scheduling VLIW Instructions |
ISCAPDCS
2004
13 years 8 months ago
2004
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
On chip memories provide fast and energy efficient storage for code and data in comparison to caches or external memories. We present techniques and algorithms that allow for an au...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
CC
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Alias analysis, traditionally performed statically, is unsuited for a dynamic binary translator (DBT) due to incomplete control-flow information and the high complexity o...