2 search results - page 1 / 1 » Effectiveness of Closure of Public Places with Time Delay in... |
JIB
2008
13 years 7 months ago
2008
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...