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» Efficient Barriers for Distributed Shared Memory Computers
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ICPP
2003
IEEE
14 years 27 days ago
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-thre...
Magnus Ekman, Per Stenström
HPCA
1998
IEEE
13 years 12 months ago
Exploiting Two-Case Delivery for Fast Protected Messaging
We propose and evaluate two complementary techniques to protect and virtualize a tightly-coupled network interface in a multicomputer. The techniques allow efficient, direct appli...
Kenneth Mackenzie, John Kubiatowicz, Matthew Frank...
HIPC
2000
Springer
13 years 11 months ago
Improving Offset Assignment on Embedded Processors Using Transformations
Embedded systems consisting of the application program ROM, RAM, the embedded processor core and any custom hardware on a single wafer are becoming increasingly common in areas suc...
Sunil Atri, J. Ramanujam, Mahmut T. Kandemir
IPPS
2010
IEEE
13 years 5 months ago
Head-body partitioned string matching for Deep Packet Inspection with scalable and attack-resilient performance
Abstract--Dictionary-based string matching (DBSM) is a critical component of Deep Packet Inspection (DPI), where thousands of malicious patterns are matched against high-bandwidth ...
Yi-Hua E. Yang, Viktor K. Prasanna, Chenqian Jiang
IPPS
2005
IEEE
14 years 1 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss