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» Efficient Barriers for Distributed Shared Memory Computers
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HPDC
1996
IEEE
14 years 2 months ago
Shared Memory NUMA Programming on I-WAY
The performance of the Global Array shared-memory nonuniform memory-access programming model is explored on the I-WAY, wide-area-network distributed supercomputer environment. The...
Jarek Nieplocha, Robert J. Harrison
HPCA
2002
IEEE
14 years 11 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...
ICPP
2009
IEEE
13 years 8 months ago
Employing Transactional Memory and Helper Threads to Speedup Dijkstra's Algorithm
In this paper we work on the parallelization of the inherently serial Dijkstra's algorithm on modern multicore platforms. Dijkstra's algorithm is a greedy algorithm that ...
Konstantinos Nikas, Nikos Anastopoulos, Georgios I...
HPCA
2002
IEEE
14 years 11 months ago
CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters
Clusters of high-end workstations and PCs are currently used in many application domains to perform large-scale computations or as scalable servers for I/O bound tasks. Although c...
Peter Jamieson, Angelos Bilas
IPPS
1998
IEEE
14 years 2 months ago
Deriving Efficient Cache Coherence Protocols through Refinement
Abstract. We address the problem of developing efficient cache coherence protocols implementing distributed shared memory (DSM) using message passing. A serious drawback of traditi...
Ratan Nalumasu, Ganesh Gopalakrishnan