303 search results - page 26 / 61 » Efficient Design Error Correction of Digital Circuits |
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
13 years 6 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
SENSYS
2003
ACM
14 years 2 months ago
2003
ACM
In the absence of location errors, geographic routing - using a combination of greedy forwarding and face routing - has been shown to work correctly and efficiently. The effects o...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Droplet-based microfluidic biochips have recently gained much attention and are expected to revolutionize the biological laboratory procedure. As biochips are adopted for the comp...