303 search results - page 35 / 61 » Efficient Design Error Correction of Digital Circuits |
ICIP
2006
IEEE
14 years 10 months ago
2006
IEEE
We present in this paper a method for implementing moment functions in a CMOS retina for shape recognition applications. The method is based on the use of binary patterns and it a...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
DATE
2010
IEEE
13 years 5 months ago
2010
IEEE
Probabilistic CMOS is considered a promising technology for future generations of computing devices. By embracing possibly incorrect calculations, the technology makes it possible ...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
TVLSI
2002
13 years 8 months ago
2002
We propose two practical approaches for on-chip inductance extraction to obtain a highly sparsified and accurate inverse inductance matrix K. Both approaches differ from previous ...