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113
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ICCAD
2007
IEEE
86views Hardware» more  ICCAD 2007»
16 years 1 months ago
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
—During the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. In this paper, we introduce several important properties of the s...
Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-C...
DSD
2008
IEEE
115views Hardware» more  DSD 2008»
15 years 11 months ago
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
We propose a method to efficiently design a “parity generator”, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designe...
Petr Fiser, Pavel Kubalík, Hana Kubatova
ICECCS
2008
IEEE
122views Hardware» more  ICECCS 2008»
15 years 11 months ago
Efficient Embedded Runtime Systems through Port Communication Optimization
Traditionally shared data areas have been used to efficiently communicate between embedded system tasks, such as periodically executing control system tasks. Such implementations ...
Peter H. Feiler
149
Voted
IPPS
2007
IEEE
15 years 11 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
130
Voted
APCCAS
2006
IEEE
261views Hardware» more  APCCAS 2006»
15 years 10 months ago
Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations
—In this paper, an area/delay efficient recoding method for parallel CORDIC (COordinate Rotation DIgital Computer) rotation algorithm is proposed. This recoding method can reduce...
Tso-Bing Juang