Due to false paths and multi-cycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing a...
It is advantageous to perform compiler optimizations that attempt to lower the worst-case execution time (WCET) of an embedded application since tasks with lower WCETs are easier ...
Wankang Zhao, William C. Kreahling, David B. Whall...
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Background: DNA instability profiles have been used recently for predicting the transcriptional start site and the location of core promoters, and to gain insight into promoter ac...
Miriam R. Kantorovitz, Zoi Rapti, Vladimir Gelev, ...
Mobile devices are becoming an inseparable part of our lives and personalized location-based mobile services are gaining more and more popularity. The scope of this paper is to il...