92 search results - page 13 / 19 » Efficient Secret Sharing with Access Structures in a Hierarc... |
HIPEAC
2011
Springer
12 years 7 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
GCC
2005
Springer
14 years 1 months ago
2005
Springer
Web caching has been well accepted as a viable method for saving network bandwidth and reducing user access latency. To provide cache sharing on a large scale, hierarchical web cac...
JPDC
2006
13 years 7 months ago
2006
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
JIIS
2002
13 years 7 months ago
2002
Although computer speed has steadily increased and memory is getting cheaper, the need for storage managers to deal efficiently with applications that cannot be held into main memo...
FPGA
2010
ACM
13 years 10 months ago
2010
ACM
Multi-ported memories are challenging to implement with FPGAs since the provided block RAMs typically have only two ports. We present a thorough exploration of the design space of...