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JUCS
2007
122views more  JUCS 2007»
13 years 7 months ago
A New Architecture for Concurrent Lazy Cyclic Reference Counting on Multi-Processor Systems
: Multi-processor systems have become the standard in current computer architectures. Software developers have the possibility to take advantage of the additional computing power a...
Andrei de Araújo Formiga, Rafael Dueire Lin...
ICS
2010
Tsinghua U.
13 years 10 months ago
The auction: optimizing banks usage in Non-Uniform Cache Architectures
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
Javier Lira, Carlos Molina, Antonio Gonzále...
EUROPAR
2010
Springer
13 years 8 months ago
Multi-GPU and Multi-CPU Parallelization for Interactive Physics Simulations
Today, it is possible to associate multiple CPUs and multiple GPUs in a single shared memory architecture. Using these resources efficiently in a seamless way is a challenging issu...
Everton Hermann, Bruno Raffin, François Fau...
DDECS
2008
IEEE
227views Hardware» more  DDECS 2008»
13 years 9 months ago
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator
The paper introduces a cryptographic System on a Chip (SoC) implementation based on recent Actel nonvolatile FPGA Fusion chip with embedded ARM7 soft-core processor. The SoC is bui...
Milos Drutarovsky, Michal Varchola
PPL
2008
124views more  PPL 2008»
13 years 7 months ago
Experimental Evaluation of BSP Programming Libraries
The model of bulk-synchronous parallel computation (BSP) helps to implement portable general purpose algorithms while keeping predictable performance on different parallel compute...
Peter Krusche