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APCSAC
2001
IEEE
15 years 8 months ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
EUROCRYPT
2000
Springer
15 years 8 months ago
Cryptanalysis of Patarin's 2-Round Public Key System with S Boxes (2R)
In a series of papers Patarin proposes new efficient public key systems. A very interesting proposal, called 2-Round Public Key System with S Boxes, or 2R, is based on the difficul...
Eli Biham
PPL
2006
81views more  PPL 2006»
15 years 4 months ago
Microthreading a Model for Distributed Instruction-level Concurrency
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
Chris R. Jesshope
ICIP
2002
IEEE
16 years 5 months ago
Optimal protection assignment for scalable compressed images
This paper is concerned with the efficient transmission of scalable compressed images over lossy communication channels. Recent works have proposed several strategies for assignin...
Johnson Thie, David Taubman
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
16 years 1 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman