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DDECS
2006
IEEE
140views Hardware» more  DDECS 2006»
13 years 11 months ago
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
Zbysek Gajda
SIPS
2008
IEEE
14 years 1 months ago
Efficient mapping of advanced signal processing algorithms on multi-processor architectures
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
Bhavana B. Manjunath, Aaron S. Williams, Chaitali ...
PDP
2003
IEEE
14 years 25 days ago
Load Balancing for Spatial-grid-based Parallel Numeric Simulations on Clusters of SMPs
Load distribution is an essential factor to parallel efficiency of numerical simulations that are based on spatial grids, especially on clusters of symmetric multiprocessors (SMPs...
Huaien Gao, Andreas Schmidt, Amitava Gupta, Peter ...
ICPP
2009
IEEE
14 years 2 months ago
Exploiting Simulation Slack to Improve Parallel Simulation Speed
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
Jianwei Chen, Murali Annavaram, Michel Dubois
IPPS
2010
IEEE
13 years 5 months ago
Acceleration of spiking neural networks in emerging multi-core and GPU architectures
Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabi...
Mohammad A. Bhuiyan, Vivek K. Pallipuram, Melissa ...