76 search results - page 4 / 16 » Efficient reachability checking using sequential SAT |
ACSD
2004
IEEE
14 years 2 months ago
2004
IEEE
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
CAV
2000
Springer
14 years 2 months ago
2000
Springer
In this paper we show how to do symbolic model checking using Boolean Expression Diagrams (BEDs), a non-canonical representation for Boolean formulas, instead of Binary Decision Di...
ICCAD
2001
IEEE
14 years 7 months ago
2001
IEEE
Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem ...
IJFCS
2006
13 years 11 months ago
2006
For successful software verification, model checkers must be capable of handling a large number of program variables. Traditional, BDD-based model checking is deficient in this re...
FMCAD
2000
Springer
14 years 2 months ago
2000
Springer
Image computation nds wide application in VLSI CAD, such as state reachability analysis in formal veri cation and synthesis, combinational veri cation, combinational and sequential...