76 search results - page 8 / 16 » Efficient reachability checking using sequential SAT |
STTT
2010
13 years 9 months ago
2010
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
DAC
1998
ACM
14 years 12 months ago
1998
ACM
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
FMICS
2008
Springer
14 years 13 days ago
2008
Springer
Different approaches have been developed to mitigate the state space explosion of model checking techniques. Among them, symbolic verification techniques use efficient representati...
GLVLSI
2009
IEEE
14 years 5 months ago
2009
IEEE
The sequential depth determines the completeness of bounded model checking in design verification. Recently, a SATbased method is proposed to compute the sequential depth of a de...
FMCAD
2008
Springer
14 years 13 days ago
2008
Springer
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...