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ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
15 years 10 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
ANSS
2008
IEEE
16 years 15 days ago
Resource Allocation Strategies in a 2-Level Hierarchical Grid System
Efficient job scheduling in grids is challenging due to the large number of distributed autonomous resources. In this paper we study various resource allocation policies in a 2-le...
Stylianos Zikos, Helen D. Karatza
ICMCS
1997
IEEE
142views Multimedia» more  ICMCS 1997»
15 years 10 months ago
A Rate Allocation Policy with MCR/PCR Support and Distributed ABR Implementation Using Explicit Rate Feedback
An important concept in the available bit rate (ABR) service model as defined by the ATM Forum is the minimum cell rate (MCR) guarantee as well as the peak cell rate (PCR) constra...
Yiwei Thomas Hou, Henry H.-Y. Tzeng, Shivendra S. ...
169
Voted
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
15 years 10 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram
150
Voted
ANSS
2004
IEEE
15 years 9 months ago
Cache Simulation Based on Runtime Instrumentation for OpenMP Applications
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...
Jie Tao, Josef Weidendorfer