555 search results - page 18 / 111 » Efficiently Implementing Episodic Memory |
INFOCOM
2002
IEEE
14 years 2 months ago
2002
IEEE
A multigigabit IP router may receive several millions packets per second from each input link. For each packet, the router needs to find the longest matching prefix in the forw...
EUROPAR
2009
Springer
14 years 1 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
CORR
2010
Springer
13 years 10 months ago
2010
Springer
Algorithms are developed for calculating dealiased linear convolution sums without the expense of conventional zero-padding or phase-shift techniques. For one-dimensional in-place ...
SPAA
2009
ACM
14 years 10 months ago
2009
ACM
In order to be efficient with selfish programmers, a multicore transactional memory (TM) system must be designed such that it is compatible with good programming incentives (GPI),...
TVLSI
2008
13 years 9 months ago
2008
Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transis...