555 search results - page 94 / 111 » Efficiently Implementing Episodic Memory |
ISPAN
1996
IEEE
14 years 23 days ago
1996
IEEE
In this paper, we have presented the design and evaluation of a compiler system, called APE,for automatic parallelization of scientific and engineering applications on distributed...
ACSD
2004
IEEE
14 years 10 days ago
2004
IEEE
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
FPL
2006
Springer
14 years 8 days ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
APCSAC
2000
IEEE
14 years 6 days ago
2000
IEEE
Dataflow computation models enable simpler and more efficient management of the memory hierarchy - a key barrier to the performance of many parallel programs. This paper describes...
PLDI
2000
ACM
14 years 5 days ago
2000
ACM
Most compiler optimizations and software productivity tools rely on information about the effects of pointer dereferences in a program. The purpose of points-to analysis is to com...