10 search results - page 1 / 2 » Eliminating Conditional Branches for Enhancing Instruction L... |
ISPAN
1996
IEEE
14 years 9 months ago
1996
IEEE
ISCAS
2005
IEEE
14 years 11 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
SCAM
2005
IEEE
14 years 11 months ago
2005
IEEE
Most software for embedded systems, including digital signal processing systems, is coded in assembly language. For both understanding the software and for reverse compiling it to...
ISCAPDCS
2003
14 years 7 months ago
2003
In modern computer systems loops present a great deal of opportunities for increasing Instruction Level and Thread Level Parallelism. Loop unrolling is a technique used to obtain ...
ISCA
1999
IEEE
14 years 10 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...