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ECRTS
2002
IEEE
14 years 17 days ago
Fully Automatic Worst-Case Execution Time Analysis for Matlab/Simulink Models
In today’s technical world (e.g., in the automotive industry), more and more purely mechanical components get replaced by electro-mechanical ones. Thus the size and complexity o...
Raimund Kirner, Roland Lang, Gerald Freiberger, Pe...
RTSS
2005
IEEE
14 years 1 months ago
WCET Centric Data Allocation to Scratchpad Memory
Scratchpad memory is a popular choice for on-chip storage in real-time embedded systems. The allocation of code/data to scratchpad memory is performed at compile time leading to p...
Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, T...
CASES
2008
ACM
13 years 9 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
ACCV
2009
Springer
13 years 11 months ago
People Tracking and Segmentation Using Efficient Shape Sequences Matching
Abstract. We design an effective shape prior embedded human silhouettes extraction algorithm. Human silhouette extraction is found challenging because of articulated structures, po...
Junqiu Wang, Yasushi Yagi, Yasushi Makihara
CASES
2001
ACM
13 years 11 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder