599 search results - page 19 / 120 » Energy and Performance Models for Synchronous and Asynchrono... |
ENTCS
2008
13 years 7 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
SIGMETRICS
1998
ACM
13 years 12 months ago
1998
ACM
In many real applications, for example those with frequent and irregular communication patterns or those using large messages, network contention and contention for message proces...
ICC
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper concerns the cross-layer design between physical layer and MAC (Multiple Access Control) layer in asynchronous wireless random access network. The proposed cross-layer d...
CF
2010
ACM
14 years 23 days ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...